With the rapid development of electronic and computer technology, radio frequency technology has been used in more and more occasions as a wireless network communication means, and has shown its unique superiority. It replaces the traditional intricate cables, enabling mobile phones, laptops, printers, copiers, keyboards and other devices in homes or offices to be interconnected, freeing people from numerous connection cables and freely forming themselves. Personal network. As a short-range wireless communication technology that replaces the data cable, it combines various data and voice devices in the home or office into a piconet, and can further interconnect to form a distributed network, thereby realizing between these connected devices. Quick and convenient communication links, so its potential for development in wireless network systems is enormous.
1 system hardware composition and working principleThe RF and digital baseband circuits are connected in a proper manner to form the hardware circuit of the designed RF transceiver application system. The overall circuit is shown in Figure 1. Among them, the arrow with the added voltage to ensure the normal operation of the circuit, its working voltage is 3 V.
The RF part circuit is mainly a radio frequency transceiver designed with TRF6900 transceiver chip and some peripheral components. The TRF6900 is a single-chip RF transceiver chip from Texas Instruments, which integrates a complete transmit and receive circuit. It operates from 850 to 950 MHz and has a supply voltage range of 2.2 to 3.6 V. The RF output power is up to +5 dBm, while the current consumption in standby mode is only O. Between 5 and 5 μA. The TRF6900 features a high throughput 16 bRISC architecture with a maximum speed of 8 MIPS. In addition, the transceiver also has FM/FSK modulation mode and uses a three-wire serial interface, so it can be easily connected to the microcontroller, which can be used for two-way wireless transmission of data in the ISM band, which can be easily applied to it. The transmission and reception are controlled, and thus applications based on it are becoming more and more common.
1.1.1 Receiving principle
The signal received from the antenna is introduced into the TRF6900 by the LNA IN, first through the low noise amplifier. The low noise amplifier provides 13 dB of gain. It has both normal and low gain modes. When the signal received by the TRF6900 is strong, the low gain mode should be selected to minimize the nonlinear distortion of the signal. The amplified signal is sent to the mixer, which converts the signal to the intermediate frequency and then amplifies through the first and second intermediate frequencies. The first stage of IF amplification yields a gain of 7 dB to compensate for the losses introduced by the filter; the second stage of IF amplification consists of multiple amplifiers for a total gain of 80 dB. After two-stage amplification, if FM/FSK modulation is used, it is sent to the FM/FSK demodulator, and the demodulated data signal is taken out from DATA OUT. In the case of frequency shift keying (ASK) or on-off keying (OOK), a received signal strength indicator (RSSI) is demodulated, and the demodulated baseband data is output from RSSI OUT.
1.1.2 How the launch works
The digital baseband signal is introduced from the TX DATA into the TRF6900 chip, modulated by the direct digital synthesizer (DDS) to the intermediate frequency, multiplied by the phase-locked loop (PLL) to the RF, and finally amplified by the power amplifier to derive the RF from the PA OUT. The signal is then transmitted through the antenna.
1.1.3 Working Principle of Serial Control Interface
The serial control interface consists of three parts: CLOCK, DATA, and STOBE. It controls all the internal registers of the TRF6900, including the DDS parameter setting registers and other control registers. On each rising edge of CLOCK, the logic value of the DATA pin is fed into the 24 b shift register. When the STOBE level is raised, the set parameters are sent to the selected latch. The TRF6900 has four programmable 24 b control words (A, B, C, D). Control words A and B control the output signal frequency in the DDS mode 0 and mode 1 states, respectively. Control word C is responsible for the setting of the phase locked loop and DDS mode O. Control word D is responsible for the modulation and setting of DDS mode 1.
1.2 digital baseband part The digital baseband section is based on the microcontroller MSP430F1121. By converting the external analog signal into a digital signal suitable for the TRF6900, it can be easily converted intelligently with the software design. The hardware circuit of the digital baseband part consists of RS 232 and MSP430F1121, as shown in Figure 1.
The MSP430F112l microcontroller is an ultra-low power, high performance 16-bit reduced instruction set MCU consisting of the following components: the base clock module, including a digitally controlled oscillator (DCO) and a crystal oscillator; The dog timer Watchdog TImer can be used as a general-purpose timer; a 16-bit timer TImer_A with three capture/compare registers; two 8-bit parallel ports with interrupt functions: P1 and P2; and an analog comparator Comparator A.
The phase detector is one of the unit modules in the phase-locked loop formed by the PPL, and the input reference frequency is determined by the output signal of the DDS. The frequency synthesizer based on DSS technology can well meet the performance of various indicators, and at the same time make the design simple. The resolution of the phase detector output frequency is:
Where: fpd is the minimum input frequency of the phase detector, and is also 2° of the DDS clock frequency fref, that is, the weight of the least significant bit. The TRF6900 DDS accumulator has 24 bits, and the fpd is multiplied by the pre-scaled value N (optional 256 or 512), which gives the minimum frequency step value:
The input of the accumulator is 24-bit user serial data (control word), the clock reference signal is used as the accumulator's working clock signal, and the two determine the resolution of the frequency; the output is a series of sampling ramp digital pulses, the null frequency is equal to the clock frequency. After D/A conversion, the sinusoidal signal fo_DSS of the analog domain is obtained, which represents the reference phase, which is the reference input signal of the phase detector. The final performance of the DDS is mainly determined by the quantization error and filtering characteristics during the D/A conversion process.
2.2.1 Clock circuit design and parameter calculation The crystal oscillator adopts the parallel resonance mode of operation, as shown in the peripheral circuits of pins 23 to 24 in Figure 1. The total phase shift of the circuit is 360°, where the inverter provides a phase shift of 180°, R7 and C22 provide a 90° lag phase, and the crystal and capacitor C1 also bring a phase lag of 90°. The crystal oscillators operating in parallel are used as inductors. The crystal access capacitor compensates for the phase shift to meet the oscillation conditions.
Polarization resistor R1 is used to set the bias point of the inverter, typically one-half the value of the Vcc pin. If R1 is too small, it will reduce the loop gain and destroy the network feedback condition. The typical value is 1~5 MΩ. You can observe the 23-pin output frequency as a function of voltage. If the crystal oscillator is overdriven, the output frequency will decrease after increasing the voltage. At this time, the resistor R2 should be fine-tuned. Note that R2 should be small enough to ensure that the oscillator can oscillate below the minimum operating voltage. C1 and the crystal's bypass capacitor Co and the input capacitance of the inverter together constitute the input capacitance of the crystal. To provide stability, the crystal's input capacitance can be selected from 20 to 30 pF.
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