The largest FPGA in the industry was born, breaking the constraints of Moore's Law

Recently, two companies also released a revolutionary breakthrough in chip packaging: one is that STMicroelectronics announced the introduction of TSV into mass production of MEMS chips; the other is Xilinx combined with TSV and micro-convex In the block process, four FPGA chips are connected side by side on a passive silicon interposer, and a programmable logic device with an equivalent capacity of 20 million gate ASICs is built. The commercialization of these new packages will change the current rules of the semiconductor industry.

Recently, two companies have also released a revolutionary breakthrough in chip packaging: One is that STMicroelectronics has announced the introduction of TSV (silicon through-hole technology) into mass production of MEMS chips, and STMicroelectronics' multi-chip MEMS products (such as smart sensors). In the multi-axis inertial module, the through-silicon via technology replaces the traditional chip interconnect method (without wire bonding) in a vertical short-circuit manner to achieve higher integration and performance in smaller-sized products. The other is that Xilinx has announced that four different FPGA chips will be connected side by side on the passive silicon interposer through Stacked Silicon Interconnect (SSI) technology. Combined with TSV technology and micro-bump technology, the equivalent capacity is 2000. Wan ASIC programmable logic device. Although the same is based on TSV technology, the former vertical stack industry is called 3D package; the latter type of interconnect stack is called 2.5D package. The successful mass production of these two different TSV packaging technologies will bring about a new game plan. Today, Moore's Law is increasingly difficult to move and new semiconductor technologies are becoming more and more expensive at 2xnm. The revolution is already the best way to surpass the opponent.

Here to explain why one is a 3D package, a 2.5D package. “At present, the industry has reached a point of view. 3D refers to vertical stacking. Micro ICs are connected with micro vias and through-silicon vias. Micro-embossing is an emerging technology. There are a lot of them. For example, if there is a stress between two silicon wafers, for example, the expansion coefficient of the two chips may not be the same, and the pressure on the middle connection of the micro-bulging surface will be very high, one expansion will be faster, and one expansion will be slower. Secondly, there will be stress in the through-silicon vias, which will affect the performance of the surrounding transistors.The third is the challenge of thermal management. If both are active ICs, heat dissipation becomes a big problem. Therefore, for a true 3D package, the industry needs to address the above three important challenges.” Tang Liren, executive vice president of Asia Pacific at Xilinx, explains: “At present, only the Memory chip can be realized in 3D packaging. STMicroelectronics' MEMS energy The 3D package is implemented because it faces smaller issues such as heat generation, but for the mobile terminal, the device size will be greatly reduced, which is also a trend.From the current situation To achieve true 3D package different complex logic between the IC, it requires at least 2--3 years. "

He went on to explain the 2.5D approach: “We combine industry partners such as TSMC and Amkor to adopt the 2.5D approach, multiple active ICs, and discharge them to passive media because the silicon interposer is passive silicon with no transistors in it. There is no TSV stress and heat dissipation problem.With multi-chip FPGA integration, the capacity can be very large, avoiding the ramp-up phase of the new process high-capacity chip, and avoiding the I/O interconnection of multiple FPGAs. Reducing power consumption substantially, for example, the integrated Virtex-7 2000T FPGA with four FPGAs introduced here consumes less than 20 W, and has a capacity equivalent to 20 million gates of the ASIC.If four monolithic FPGAs are used separately, the power consumption will increase. Far more than this number, it may be several times the value."

SSI is a revolutionary step forward in the traditional SIP technology and can be said to be closer to a single chip. Pins are still needed for chip-to-chip interconnections during SIP stacking, while TSVs incorporate microbumps to remove leads. This is a major breakthrough for FPGA/PLD, and even CPUs with many I/O interfaces. The power consumption is greatly reduced, the signal delay is reduced, and the integration complexity is also reduced. “This is a transcendence of Moore's Law.” Tang Liren pointed out, “When a new generation of processes is used, the higher the die, the lower the yield and the exponential decline. In general, it takes 1-2 years to be good. The rate is raised to a higher level, however, if the chip size is small, the yield rate can be easily increased, so if several small-size FPGAs can be integrated together, the capacity and performance can be significantly increased. The cost can also be well controlled, while power consumption and performance are improved.” With the SSI technology, the newly introduced Virtex-7 2000T FPGA integrates 6.8 billion transistors, equivalent to 20 million gate ASICs. For customers, the great significance is that if this new technology is not adopted, it will be possible to achieve such a large transistor capacity in a single FPGA, at least until the next generation of process technology. Instead of using ASICs today, a single FPGA solution can achieve the functionality of 3-5 FPGA solutions, thereby significantly reducing costs. "We can design prototypes and build system simulators for customers at least one year in advance," he said. This is a great advantage for companies that need large-scale ASICs in the wireless communications and optical communications core areas, because it takes about 50 million US dollars to open a 28nm ASIC. In addition to these very high-end communication applications, Xiu-qing Zhang, Director of Sales and Marketing for Xilinx Asia Pacific, revealed: “Now Japanese manufacturers have used it to design naked-eye 3D TV core chips because the algorithm will be quite complicated when using multi-view. The Virtex-7 2000T exactly meets their requirements.” It is reported that the Virtex-7 2000T has now received more than 2,000 design orders, and the first engineering samples have also begun to supply.

"For users, the Stacked Silicon Interconnect (SSI) chip is equivalent to a large FPGA chip, completely transparent to the user." Zhang Yuqing explained, "The Xilinx ISE design kit can automatically assign the design to the FPGA chip. Without any user intervention, the customer can also perform logic layout planning on a specific FPGA chip if desired, and software tools allow the algorithm to intelligently place related logic within the FPGA chip and follow inter-chip and intra-chip connections if not required by the user. And timing rules. The ISE design tools that support the new SSI package are already available to early adopters. We also provide some design rule check (DRC) and software information to guide the user on how to place and route the logic between the new FPGA chips."

The significance of Xilinx and TSMC and Amkor's 2.5D package introduction is not just the on-chip stacking of multiple FPGAs. It can be extended to more kinds of complex chip on-chip stacks, such as FPGAs and CPUs, or FPGAs and high speeds. Transceivers, etc., opened a door to allow the industry to embark on a new journey that could surpass Moore's Law and quickly provide large-scale and complex chips while reducing power consumption and costs.