In high-speed real-time or non-real-time signal processing systems, the use of large-capacity memory to implement data caching is an indispensable link, and also one of the key and difficult points in the implementation of the system. SDRAM (Synchronous Dynamic Random Access Memory) has the advantages of low price, high density, and fast data read and write speed, thus becoming the preferred storage medium sanction for data caching. However, the structure of SDRAM memory is quite different from that of RAM, and its control timing and mechanism are also complicated, which limits the use of SDRAM. At present, although some capable microprocessors provide transparent interfaces with SDRAM, their scalability and flexibility are not enough to meet the requirements of real systems, which limits the use of SDRAM.
On the premise of reading the SDRAM data files in detail, referring to the IP core of ALTERA, a general-purpose SDRAM controller is designed using programmable devices (CPLD, FPGA). It has high flexibility and can be easily combined with other data acquisition and analysis systems, as shown in Figure 1. In this system, SDRAM memory array caches high-speed data from intermediate frequencies. After being full, the data is read out to the data processing module slowly. The design of the SDRAM control module will be described in detail below.
1 Structure of SDRAM memory
The SDRAM memory module is composed of SDRAM memory chips, and the number of memory chips on the memory module is determined according to the capacity of the memory module. Now take the TIM16LSDT6464A SDRAM memory stick produced by MICRON as an example to briefly introduce the structure of SDRAM.
The MIT16LSDT6464A memory module has a capacity of 512M Byte and is composed of 16 memory chips MT46LC32M8A2 with a capacity of 32M Byte. The 16 memory chips are divided into two levels, the data bit width of each chip is 8 bits. A group of 8 chips, and the data width of 64 bits. The data lines and controls of each memory chip are multiplexed. The read and write operations to the memory module are based on the memory chipset, and the group number is determined by the chip selection signals S0, S1, S2, and S3 of the memory module. S0, S2 control chipset 1, S1, S3 control chipset 2.
The main signals of the SDRAM memory chip are control signals, control signals, and data signals, all of which are synchronous input and output signals of the working clock.
The main control signals are: CS (chip select signal), CKE (clock enable signal), DQM (input and output enable signal), CAS, RAS, WE (read and write control command word). Through various logic combinations of CAS, RAS and WE, various control commands can be generated.
Address signals are: BA0 and BA1 page address selection signals, A0 ~ A12 address signals, row and column address selection signals. Time-division multiplexing determines whether the address is a row address or a column address. In the read-write operation, the page address, row address, and column address are given in sequence on the ground line, and the memory cell address is finally determined.
The data signals are: DQ0 ~ DQ7, bidirectional data. Its enablement is controlled by DQM.
The working mode of SDRAM is selected by setting the working mode register by the LOAD MODE REGISTER command. The setting parameters are Reserved (Reserve), Write Burst Mode (WB, Write Burst Mode), Operation Mode (Op Mode, Working Mode), CAS Latency (CAS Delay), Burst Type (BT, Burst Type), Burst Length (Burst length).
2 SDRAM basic read and write operations
The basic read operation of SDRAM requires the control line and address line to issue a series of commands to complete. First issue the BANK activation command (ACTIVE), and latch the corresponding BANK address (given by BA0, BA1) and row address (given by A0 ~ A12). After the BANK activation command must wait for more than tRCD (SDRAM's RAS to CAS delay index) time before issuing the read command word. After CL (CAS delay value) working clock, the read data appear on the data bus in sequence. At the end of the read operation, a precharge (PRECHARGE) command is issued to the SDRAM to close the activated page. Wait for the tRP time (PRECHARGE) command to close the activated page. After waiting for tRP time (after PRECHAREG command, you can access the line again after tRP time), you can start the next read and write operation. The read operation of SDRAM only has Burst Mode (Burst Mode), and the burst length is 1, 2, 4, 8 optional.
The basic write operation of SDRAM also requires the control line and address line to issue a series of commands to complete. First issue the BANK activation command (ACTIVE), and latch the corresponding BANK address (given by BA0, BA1) and row address (given by A0 ~ A12). After the BANK activates the command, it must wait for a time greater than tRCD before issuing the write command word. The write command can be written immediately, and the data to be written is sent to the DQ (data line) in sequence. Delay the tWR time after the last data is written. Issue a pre-charge command to close the page that has been activated. After waiting for tRP time, you can start the next operation. There are two types of write operations: burst write and non-burst write. The burst length is the same as the read operation.
For the specific requirements of tRCD, tRP and tWR, please refer to the data manual provided by the SDRAM manufacturer. The number of working clocks waiting is determined by the minimum value of tRCD, tRP, tWR and the working clock period.
It can be drawn from the above introduction that the read and write operations of SDRAM are composed of a series of commands, so the read and write operations are clock loss, and the working clock rate is not equal to the read and write rates that SDRAM can reach. However, because SDRAM has burst read and write modes, that is to say, a series of consecutive address data can be read and written, thereby improving efficiency. When the burst length is a full page, the read and write speeds reach the fastest. The calculation formula of random read and write speed is:
furite / read = working clock frequency (HzHzHhdkkdk ss dkkdkdkd ,,,, m, mddddd) × data width (bytes) × burst read / write length / number of clocks required for operation
In order to improve storage density, SDRAM uses silicon capacitors to store information. There will always be leakage current in the capacitor, so in order not to lose information, the capacitor must be regularly refreshed and charged. The external control logic must periodically issue refresh commands to the memory module as required to ensure that each unit is refreshed within the specified time.
3 Initial operation
SDRAM must be initialized after power on, the specific operations are as follows:
(1) The system must wait for 100 ~ 200μs after power-on. After the waiting time expires, at least one empty operation or instruction prohibition operation is performed.
(2) Execute PRECHARGE command on all chips to complete pre-charging.
(3) Send two AUTO REFRESH commands to each group of memory chips, so that the refresh counter inside the SDRAM chip can enter the normal operating state.
(4) Execute the LOAD MODE REGISTER command to complete the setting of the SDRAM working mode.
After completing the above steps, SDRAM enters a normal working state, waiting for the controller to read, write, and refresh operations.
Flexible cable, also known as flex cable or flexible flat cable (FFC), is a type of electrical cable that is made up of multiple thin and flat conductive wires. These wires are usually insulated and are arranged in a parallel configuration, allowing the cable to bend and flex easily.
Flexible cables are commonly used in applications where space is limited or where frequent movement or flexing is required. They are often found in electronic devices such as laptops, smartphones, and cameras, where they are used to connect various components and circuits together.
The flexibility of the cable is achieved by using materials with high flexibility and low resistance to bending, such as polyimide or polyester. These materials allow the cable to bend without breaking or damaging the conductive wires inside.
Flexible cables come in various sizes and configurations, depending on the specific application. They can have different numbers of conductive wires, different widths, and different lengths. The connectors at the ends of the cable can also vary, depending on the devices or components that need to be connected.
Overall, flexible cables offer a convenient and reliable solution for connecting components in electronic devices that require flexibility and frequent movement. They provide a compact and space-saving design while maintaining good electrical conductivity.
PVC Coated Copper Flexible Cable,Pvc Insulated Power Cables,Multi Copper Core PVC Power Cables,Copper Conductor PVC Outer Sheath Cable
Ruitian Cable CO.,LTD. , https://www.rtlinecable.com