Random changes require new methods, new tools, and collaboration between different companies.
Extreme ultraviolet (EUV) lithography is approaching production, but random changes, also known as random effects, are resurfaced and present more challenges for this long-awaited technology.
GlobalFoundries, Intel, Samsung and TSMC hope to add EUV lithography to 7nm and 5nm production. But as before, EUV consists of several components that must be integrated before the chip maker can introduce it. Including lithography machine, light source, photoresist and mask. Recently, the industry has begun to issue alarms about quantum random effects, which can cause random changes in lithographic patterns.
Some components are ready, while others are slow to develop. In fact, for the first time, the EUV team listed photoresist and its related issues as the biggest challenge of EUV, exceeding the power supply. After years of delay, the EUV source power finally meets the requirements of high volume production (HVM).
Photoresist is a photopolymer used to make patterns, which is one of the main culprits in causing random effects. By definition, random effects describe events with random variations in photons. They are unpredictable and have no stable patterns.
In the case of EUV, photons hit the photoresist and cause a photochemical reaction. However, for EUV photoresists, new different reactions may occur during each or more reactions due to quantum delocalization. Therefore EUV is prone to random effects. In general, the industry blames the randomness mainly on photoresist, but the EUV photomask and other parts (the EUV photon mean free path is larger) may also have random variables.
The random effects are not new. In fact, this phenomenon has been plaguing the EUV team for many years. It is well known that random effects can cause variations in lithographic patterns. The industry has been working hard to solve this problem, but people either underestimate the problem, or fail to solve the problem in time, or both.
The new situation is that the industry has finally ushered in another problem. An advanced logic chip integrates one billion or more tiny vias. If a problem occurs during EUV lithography, the chip may suffer from failure or defect due to random effects (contact missing). In other words, a chip may fail due to a defect in a contact via.
This may be a wishful thinking, but chipmakers believe they can evade the potential randomness of the 7nm process node. In fact, EUV may appear at the 7nm process node. But in the case of 5nm or even 7nm process nodes, chip makers may not be able to avoid these and other problems unless there are some new breakthroughs in the industry. Harry Levinson, senior researcher and senior technical research director at GlobalFoundries, said: "Fairly, our industry is very optimistic about our direction toward EUV lithography. We are preparing to introduce the first generation into mass production, looking forward to the second Generation of EUV lithography, resistance to random effects is definitely one of the most important issues."
Regardless of the node, EUV random effects cause problems for chip manufacturers, fab tool suppliers, and IC design groups. David Abercrombie, Director of DFM Program at Siemens, said: "From a design perspective, the random effects are indeed random because you can't predict the location and number of changes. Therefore, there is no systematic way to say that a particular layout feature should be in this. The region is modified in another region. In other words, in addition to all the sensitive features avoided, turning it into a traditional design rule constraint, there is absolutely no way to compensate for the effects of random effects in the design process."
In response, the industry is taking steps to address some of the issues. These include:
• Suppliers are improving EUV photoresist.
• Applied Materials and ASML are developing a new electron beam measurement tool that promises to detect random defects. In addition, the startup Fractilia has designed a method to aid measurement.
• Then, with these new measurement data, chipmakers request competitive fab tool suppliers to collaborate and integrate information together.
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